1. Field
The present disclosure pertains to memory devices with improved writeability of memory cells at low voltage levels.
2. Background
With increased scalability of semiconductor devices, two goals are to make such semiconductor devices more dense and power efficient. Lowering the operating voltage is sometimes used to achieve power efficiency. In the case of memory devices, the lowered voltage may cause reliability issues when writing to memory cells due to unstable behavior of transistors therein.
FIG. 1 illustrates a conventional memory cell 102 comprising a cell core 114 (first inverter 104, and second inverter 106), a first write transistor 108, a second write transistor 110, and a pair of read access transistors 112. FIG. 2 illustrates a detailed implementation of part of the memory cell 102 of FIG. 1. In one example, the memory cell 102 may be a volatile memory.
The cell core 114 may include a first inverter 104, including a first driver transistor 206 (FIG. 2, pull-down transistor) and a first load transistor 208 (pull-up transistor), and a second inverter 106, including a second driver transistor 202 (pull-down transistor) and a second load transistor 204 (pull-up transistor). In this example, the load transistors 204 and 208 (pull-up transistors) are P-channel metal-oxide-silicon (PMOS) transistors and the driver transistors 202 and 206 (pull-down transistors) are N-channel metal-oxide-silicon (NMOS) transistors. The bit cell 102 may be coupled to a write bitline (WBL) 118, a write bitline bar (WBLB) 120, and a write wordline (WWL) 116 that operate together to store one bit of information in the cell core 114. When the write wordline (WWL) 116 is asserted (i.e., goes to a high state), the states at the write bitline (WBL) 118 and the write bitline bar (WBLB) 120 are stored in the cell core 114. The bit cell 102 may also be coupled to a read bitline (RBL) 122 and a read wordline (RWL) 124 that operate together to read one bit of information from the cell core 114. When both the read bitline (RBL) 122 and read wordline (RWL) 124 are asserted (e.g., goes to a high state), a bit is read through the read access transistors 112. In some exemplary implementations, the wordlines WWL 116 and RWL 124, and the bitlines WBL 118, WBLB 120, and RBL 122 may be shared among a plurality of bit cells such that just one bit cell is selected from the plurality of bit cells by a particular combination of wordline and bitline.
The first inverter 104 has its output coupled to the drain of the second write transistor 110 at Node-B. For instance, as illustrated in FIG. 2, the drain of the first load transistor 208, the source of the first driver transistor 206, and the drain of the second write transistor 110 are coupled at Node-B. The gate of the first driver transistor 206 and the gate of the first load transistor 208 are coupled together to the output (i.e., Node-A) of the second inverter 106.
Similarly, the second inverter 106 has its output coupled to the drain of the first write transistor 108 at Node-A. For instance, as illustrated in FIG. 2, the drain of the second load transistor 204, the source of the second driver transistor 202, and the drain of the first write transistor 108 are coupled at Node-A. The gate of the second driver transistor 202 and gate of the second load transistor 204 are coupled together to the output (i.e., Node-B) of the first inverter 104. Thus, in this conventional manner the first inverter 104 and second inverter 106 are cross-coupled, meaning that the output of each inverter is connected to the input of the other, to form the cell core 114 that stores a single bit of information.
The drain of the first write transistor 108 is connected to the output of the second inverter 106 (i.e., Node-A). Similarly, the complimentary second write transistor 110 is coupled to the output of the first inverter 104 (i.e., Node-B). The gates of the second write transistor 110 and first write transistor 108 are each connected to a write wordline (WWL) 116. Together, the second write transistor 110 and the first write transistor 108 form a write circuit that imposes a state on the memory cell 102 in cooperation with the WWL 116, a write bit-line (WBL) 118 and a complementary write bit-line (WBLB) 120.
If the WBL 118 is set to a value of Vdd (logical 1 or high) while the WBLB 120 is set to a value of Vss (logical 0 or low), then, when the WWL 116 is asserted (set to Vdd, high or logical 1), the output Q (Node-A) of the second inverter 106 will be set to a value of Vdd-Vtn, where Vtn is the threshold voltage of the first write transistor 108, while the output Q-Bar (Node-B) of the first inverter 104 will be set to Vss. This is because the second write transistor 110 (e.g., an NMOS transistor) starts in a saturation region of operation and ultimately operates in a linear region when its drain-source voltage Vds=0. The second load transistor 204 (e.g., PMOS) of the second inverter 106 restores Node-A to full Vdd once Node-B reaches Vss.
Conversely, if WBL 118 is set to Vss (logical 0 or low) and WBLB 120 set to Vdd (logical 1 or high), when the WWL 116 is asserted (set to Vdd, high, or logical 1), the output Q (Node-A) of the second inverter 106 will be set to a value of Vss, while the output Q-Bar (Node-B) of the first inverter 104 will be set to Vdd-Vtn, where Vtn is the threshold voltage of the second write transistor 110. The first load transistor 208 (e.g., PMOS) of the first inverter 104 restores Node-B to full Vdd once Node-A reaches Vss.
In the situation in which Node-A is initially at Vdd (e.g., high or logical 1), WBL 118 is set to Vss (logical 0 or low), and WWL 116 is enabled (e.g., Vdd, high or logical 1), writeability of the memory cell 102 of FIG. 1 involves a fight between the first write (NMOS) transistor 108 and the second load (pull-up PMOS) transistor 204. The first write transistor 108 has to be strong enough to cause Node-A to discharge to Vss while the second load transistor 204 is trying to retain Node-A at Vdd (e.g., high or logical 1).
Similarly, in the situation in which Node-B is initially at Vdd (e.g., high or logical 1), WBLB 120 is set to Vss (logical 0 or low), and WWL 116 is enabled (set to Vdd, high, or logical 1), writeability of the memory cell 106 of FIG. 1 involves a fight between the second write transistor 110 and first load transistor 208. The second write transistor 110 has to be strong enough to cause Node-B to discharge to Vss while the second load transistor 204 is trying to retain Node-B at Vdd (e.g., high or logical 1). Hence, the write transistors 108 and 110 are usually stronger than the load (pull-up) transistors 204 and 208.
FIG. 3 illustrates the conditions of writeability for the memory cell 102 of FIGS. 1 & 2 at a nominal Vdd source voltage. These graphs illustrate the conditions at the bitlines WBL 118 and WBLB 120 and outputs Q (Node-A) and Q-Bar (Node-B) during a write operation when the wordline (WWL) 116 is switched from low (e.g., logical 0 or nominal Vss voltage) to high (e.g., logical 1 or nominal Vdd voltage). When the WBL 118 is set to low (e.g., logical 0 or Vss) while the WBLB 120 is set to high (e.g., logical 1 or Vdd), and then the WWL 116 is asserted (set to high, Vdd, or logical 1), the output Q (Node-A) of the second inverter 106 will be set to a value of Vdd (e.g., logical 1 or high), while the output Q-Bar (Node-B) of the first inverter 104 will be set to Vss (e.g., logical 0 or low).
FIG. 4 illustrates the condition of writeability for the memory cell 102 of FIG. 1 at a low source Vdd voltage (Vddlow). The low source Vdd voltage (Vddlow) may occur, for example, when a device enters a power conservation state in which a lower source voltage is used, when a device uses a lower voltage power source (e.g., a portable or mobile device), and/or when a source voltage from a portable power source (e.g., battery) diminishes (e.g., as the battery drains). For the same write operation illustrated in FIG. 3, but at the lower Vddlow voltage, it can be seen that the outputs Q (Node-A) and Q-Bar (Node-B) may not reach the correct state (i.e., the outputs Q and Q-Bar do not change logical states when the WBL and WBLB change logical states).
Under normal source voltage Vdd, in order to write into the memory cell 102, the write transistors 108 and 110 may be stronger than the load transistors 204 and 208 (pull-up transistors) and/or the write transistors 108 and 110 may be the same strength/size as the driver transistors 202 and 206 (pull-down transistors) of the inverters 104 and 106 in order to write the correct bit.
However, at a low voltage of Vddlow the write transistors 108 and 110 might not be stronger than the load transistors 204 and 208 (pull-up transistors) and/or driver transistors 202 and 206 (pull-down transistors). For instance, at low voltage of Vddlow when a write operation is attempted with WBL=low and WBLB=high, the gate of the first write transistor 108 may be lowered to Vddlow which may just exceed the NMOS threshold voltage Vtn by not more than a few hundred milli-volts (mV).
If a low source voltage Vddlow is used at the gate of the first write transistor 108, the gate-to-source voltage Vgs for the first write transistor 108 may be approximately the threshold voltage Vtn, then the resistance across the first write transistor 108 (which is very weakly turned ON) is very high compared to the resistance across the first load transistor 204. Also, when the low source voltage Vddlow is used (e.g., Vgs˜Vtn), the current through the first write transistor 108 is very low compared with the current through the first write transistor 108 when typical source voltage Vdd is used. Consequently, the first write transistor 108 cannot drive the voltage at Node-A to low (e.g., Vss or logical 0) because the first load transistor 204 (pull-up transistor) is stronger (e.g., less resistive) than the first write transistor 108. As a result, the stronger first load transistor 204 maintains Node-A (Q) at high (e.g., logical 1 or Vdd) as illustrated in FIG. 4.
Similarly, if a low source voltage Vddlow is used at the gate of the second write transistor 110, the second write transistor 110 may not be able to drive the voltage at Node-B (Q-Bar) high (Vdd or logical 1) because the first driver transistor 206 (pull-down transistor) may be stronger than the second write transistor 110. As a result, the stronger first driver transistor 206 maintains Node-B (Q-Bar) at low (logical 0 or Vss) as illustrated in FIG. 4. Thus, such low voltage conditions may inhibit the proper operation of memory cells.
Consequently, a solution is needed that allows memory cells to operate correctly at lowered voltages.